Temperatures on wires in a chip are critical information in determining the allowable currents in wires to meet the expected Mean-Time-To-Failure (MTTF) as described in Black's equation (as illustrated in diagram 100 of FIG. 1), to predict reliability failure from Electromigration (EM) phenomenon in metal wire which generates undesired open or short of circuits over time of uses. Temperatures on wires/devices also have impacts on power (particularly leakage power, a strong function of temperature), resistance, EM limit, and consequently on timing, IR/dynamic voltage drop, and signal integrity.
Accurate temperature (steady-state) on wire is not easy to predict due to layout geometry complexity of the modern chips, affected by the following factors:                Local wire temperature rises due to Joule-heating power from its average or root-mean-square (rms) current and thermal coupling among wires, where the local Joule-heating power is defined as I*I*Rwire and I (current) can be Iavg on power/ground wire or Inns on signal wire;        Self-heating or local temperature rise from CMOS devices with devices in switching or idle mode; and        Thermal environment of the chip in package with complex thermal conductivity distribution and multiple die heating, e.g., in 3D-IC, and variations of the Chip-Package-System (CPS) configurations.        